sp720 the sp720 is an array of scr/diode bipolar structures for esd and over-voltage protection to sensitive input circuits. the sp720 has 2 protection scr/diode device structures per input. a total of 14 available inputs can be used to protect up to 14 external signal or bus lines. over-voltage protection is from the in (pins 1-7 and 9-15) to v+ or v-. the scr structures are designed for fast triggering at a threshold of one +v be diode threshold above v+ (pin 16) or a -v be diode threshold below v- (pin 8). from an in input, a clamp to v+ is activated if a tran- sient pulse causes the input to be increased to a voltage level greater than one v be above v+. a similar clamp to v- is activated if a negative pulse, one v be less than v-, is applied to an in input. standard esd human body model (hbm) capability is: features ? esd interface capability for hbm standards - mil std 3015.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kv - iec 61000-4-2, direct discharge , single input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv (level 2) two inputs in parallel . . . . . . . . . . . . . . . . . . . . . . . . 8kv (level 4) - iec 61000-4-2, air discharge . . . . . . . . . . . . . . . . . 15kv (level 4) ? high p eak current capability - iec 61000-4-5 (8/20 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a - single pulse, 100? pulse width. . . . . . . . . . . . . . . . . . . . . . . ?a - single pulse, 4? pulse width. . . . . . . . . . . . . . . . . . . . . . . . . ?a ? designed to provide over-voltage protection - single-ended voltage range to . . . . . . . . . . . . . . . . . . . . . . +30v - differential voltage range to. . . . . . . . . . . . . . . . . . . . . . . . . ?5v ? fast switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns risetime ? lo w input leakages . . . . . . . . . . . . . . . . . . . . . . . . . 1na at 25 o c (t yp) ? low input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pf (typ) ? an array of 14 scr/diode pairs ? operating temperature range . . . . . . . . . . . . . . . . . . . . -40 o c to 105 o c applications ? microprocessor/logic input protection ? data bus protection ? analog device input protection ? v oltage clamp functional block diagram ref er to figure 1 and t able 1 for further detail. refer to application note an9304 and an9612 for additional information. ordering information pinout sp720 (pdip, soic) top view tvs diode arrays 233 www .littelfuse .com 5 t v s d i o d e a r r a y s electronic protection array for esd and overvoltage protection v+ 16 1 8 2 3 - 7 9 - 15 in in in v- part no. temp. range ( o c) package pkg. min.
order no. sp720ap -40 to 105 16 ld pdip e16.3 1500 1970 2500 SP720AB -40 to 105 16 ld soic m16.15 SP720ABt -40 to 105 16 ld soic tape and reel m16.15 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in in in in in in v- in v+ in in in in in in in h bm standard mode r c esd (v) iec 61000-4-2 air 330 150pf >15kv direct 330 150pf >4kv direct, dual pins 330 150pf >8kv mil-std-3015.7 direct, in-circuit 1.5k 100pf >15kv
234 www.littelfuse.com sp720 tvs diode arrays electronic protection array for esd and overvoltage protection esd capability esd capability is dependent on the application and defined test standard. the evaluation results for various test standards and methods based on figure 1 are shown in table 1. for the odified mil-std-3015.7 condition that is defined as an n--ircuit method of esd testing, the v+ and v- pins have a return path to ground and the sp720 esd capability is typically greater than 15kv from 100pf through 1.5k . by strict definition of mil-std-3015.7 using in--o--in de vice testing, the esd v oltage capability is g reater than 6kv . the mil-std-3015.7 results were determined from at&t esd test lab measurements. the hbm capability to the iec 61000-4-2 standard is greater than 15kv for air discharge (level 4) and greater than 4kv for direct discharge (level 2). dual pin capability (2 adjacent pins in parallel) is well in excess of 8kv (le v el 4). f or esd testing of the sp720 to eiaj ic121 machine model (mm) standard, the results are typically better than 1kv from 200pf with no series resistance. absolute maximum ratings continuous supply voltage, (v+) - (v-). . . . . . . . . . . . . . . . . . . . . . . . . +35v forward peak current, i in to v cc , i in to gnd (refer to figure 6) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?a, 100? esd ratings and capability (figure 1, table 1) load dump and reverse battery (note 2) thermal information thermal resistance (typical, note 1). . . . . . . . . . . . . . . . . . . . . ja ( o c/w) pdip package .............................................90 soic package ...........................................130 maximum storage temperature range . . . .. . . . . . . . . . . . . . . -65 o c to 150 o c maximum junction temperature (plastic package) . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . .. . . . . . .. . . . . . . . . .300 o c (soic lead tips only) c aution: stresses above those listed in bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. no te: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications t a = -40 o c to 105 o c; v in = 0.5v cc , unless otherwise specified t able 1. esd test conditions parameter
symbol
test
conditions
min
typ
max
units
operating
voltage
range,
v supply
= [(v+) - (v-)]
v suppl
y - 2 to 30
-
v
forward
voltage
drop:
in
t o v-
in
t o v+
v fwdl
v fwdh
i in
= 1a
(peak
pulse)
-- 2 2 - - v v input
leakage
current
i
in
-20
5
20
na
quiescent
supply
current
i
quiescent
- 50
200
na
equivalent
scr
on threshold
note
3 - 1.1 - v equivalent
scr
on resistance
v
fwd
/i
fwd
; note
3 - 1 - input
capacitance
c
in
3p
f input
switching
speed
t
on
2n
s no
tes:
2.
in
automotive
and
battery
operated
systems,
the
power
supply
lines
should
be externally
protected
f or load
dump and reverse
b attery.
when
t he v+
and
v-
pins
are
connected
to the
same
supply
voltage
source
as
the
device
or control
line
under
protection,
a current
l imiti ng resistor
should be
connected
in series
between
the
external
supply
and the sp720
supply
pins to limit reverse
battery
current
to within
the
rat
ed maximum
limits.
bypass
capacitors
of typically
0.01
f or larger
f rom the v+
and
v-
pins
to ground
are
recommended.
3.
refer
to the
figure
3 graph
f or
definitions
of equivalent
cr
on threshold
and
cr
on resistance.
these
characteristics
a re given
here
for
thumb-rule
i nformation
to determine
peak
current
and dissipation
under
eos
conditions.
- - - - h.v
. suppl
y v d in
dut
c d r 1 iec 1000-4-2:
r 1 50 to 100m
r d charge
switch
discharge
switch
mil std 3015.7:
r 1 1 to 10m
figure
1.
electr
ost
a t ic discharge
test standard type/mode r d c d v d mil std 3015.7 modified hbm 1.5k 100pf 15kv standard hbm 1.5k 100pf 6kv iec 61000-4-2 hbm, air discharge 330 150pf 15kv hbm, direct discharge 330 150pf 4kv hbm, direct discharge, two parallel input pins 330 150pf 8kv eiaj ic121 machine model 0k 200pf 1kv
tvs diode arrays 235 www .littelfuse .com 5 t v s d i o d e a r r a y s e lectronic protection array for esd and overvoltage protection sp720 figure
2.
lo
w current
scr for w ard
v o l t a ge dr
op
cur
ve
figure
3.
high
current
scr
for
w ard
v o l t a ge dr
op cur
ve
6 00
800
1000
1200
f or
w ard scr
v ol t a ge dr op (mv)
1 00
80
60
40
2 0 0 f o r w a r d s c r c u r r e n t ( m a ) t a = 25
o c s ingle pulse
2.5
2 1 .5
1 0.5
0 f o r w a r d s c r c u r r e n t ( a ) t a = 25
o c s ingle pulse
v fwd
i fwd
01
2 3 for
w ard scr v ol t a ge dr op (v) equiv
. sa t . on t hreshold ~ 1.1v
figure
4.
typical
applica tion
of the sp720 as an
input
clamp
for
o ver-v o l t a ge, grea ter than 1v be
abo
ve
v+
or less
than -1v
be
belo
w v - +v
c c +v
c c input
drivers
pr
o tection circuit
(1 of 14 on chip)
sp720 input
or
signal
sources
in 9-15
in 1-7 sp720
v-
t o +v
cc
linear or
digit
al ic interf
a ce v+
tvs diode arrays 236 www.littelfuse.com sp720 electronic protection array for esd and overvoltage protection p eak transient current capability of the sp720 the peak transient current capability rises sharply as the width of the current pulse narrows. destructive testing was done to fully evaluate the sp720s ability to withstand a wide range of transient current pulses. the circuit used to generate current pulses is shown in figure 5. the test circuit of figure 5 is shown with a positive pulse input. for a negative pulse input, the (-) current pulse input goes to an sp720 n input pin and the (+) current pulse input goes to the sp720 v- pin. the v+ to v- supply of the sp720 must be allowed to float. (i.e., it is not tied to the ground reference of the current pulse generator.) figure 6 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. the maximum peak input current capability is dependent on the v+ to v- voltage supply level, improving as the supply voltage is reduced. values of 0, 5, 15 and 30 voltages are shown. the safe operating range of the tr ansient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in figure 6. when adjacent input pins are paralleled, the sustained peak current capability is increased to near ly twice that of a single pin. f or compar i- son, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. the overstress curve is shown in figure 6 for a 15v supply condition. the dual pins are capable of 10a peak current for a 10 s pulse and 4a peak current for a 1ms pulse. the complete for single pulse peak current vs. pulse width time ranging up to 1 second are shown in figure 6. 0.001 0.01 0.1 1 pulse width time (ms) p e a k c u r r e n t ( a ) 10 7 6 54 3 2 1 0 0v 5v 15v v+ to v- supply 100 1000 10 9 30v 15v caution: safe operating conditions limit of the values shown on each curve. pulse width to be no greater than 75% the maximum peak current for a given single pin stress curves dual pin stress curve 8 figure 6. sp720 typical single pulse peak current curves showing the measured point of over-stress in amperes vs pulse time in milliseconds (t a = 25 o c) + - current s ense vo ltag e probe 14 15 16 9 1 3 1 2 11 10 1 2 3 4 5 7 6 8 in i n in in i n in v- i n v+ in i n in in ini n i n + - r 1 ~ 10 typical sp720 v g v g adj. 10v/a typical r 1 (-) (+) c1 ~ 100 f c 1 v ariable time duration current pulse generator figure 5. typical sp720 peak current test circuit with a variable pulse width input
tvs diode arrays 237 www .littelfuse .com 5 t v s d i o d e a r r a y s electronic protection array for esd and overvoltage protection sp720 dual-in-line plastic packages (pdip) e16.3 (jedec ms-001 bb issue d) 1 6 lead dual-in-line plastic package no
tes:
1.
controlling
dimensions:
i nch. in case
of
conflict
between
english
and
metric
dimensions,
the inch
dimensions
control.
2.
dimensioning
and tolerancing
per
ansi y14.5m
- 1982.
3.
symbols
are
defined
in the
o
series
symbol
list
in section
2.2
of publication
no.
95.
4.
dimensions
a,
a1 and
l are measured
with the package
seated
in je-
dec
seating
plane
gauge
gs - 3.
5.
d,
d1,
and
e1 dimensions
do not
include
mold
flash
or protrusions.
mold
flash
or
protrusions
shall
not
exceed
0.010
i nch (0.25mm).
6.
e
and
are
measured
with
the
leads
constrained
to be perpendic-
ular
to datum
.
7.
e
b and
e c are
measured
at
the
lead
tips
with the
l eads
unconstrained.
e c must
be
zero
or
greater.
8.
b1
maximum
dimensions
do not
i nclude dambar
protrusions.
dambar protrusions
shall
not
exceed
0.010
i nch (0.25mm).
9.
n
is the
maximum
number
of terminal
positions.
10.
corner
leads
(1, n, n/2 and
n/2
+ 1) for
e8.3,
e16.3,
e18.3,
e28.3,
e42.6
will have
a b1 dimension
of
0.030
- 0.045
i nch (0.76
- 1.14mm).
e a -c-
c l e e a c e b e c -b-
e1
index
1 2 3 n/2
n a rea
sea
ting
b ase
p lane
plane
-c-
d1
b1
b e d d 1 a a2
l a 1 -a-
0.010 (0.25)
c
a
m bs
symbol inches millimeters notes m in max min max a - 0.210 - 5.33 4 a 1 0.015 - 0.39 - 4 a 2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n169 16
tvs diode arrays 238 www.littelfuse.com sp720 electronic protection array for esd and overvoltage protection small outline plastic packages (soic) m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes m in max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - no
tes:
1.
symbols
are
defined
in the
o series
symbol
list
in section 2.2 of
publication
number
95.
2.
dimensioning
and tolerancing
per
ansi y14.5m
- 1982.
3.
dimension
does not
include
mold
flash,
protrusions
or gate
burrs.
mold
flash,
protrusion
and
gate
burrs
shall not
exceed
0.15mm (0.006
inch)
per
side.
4.
dimension
e does not include
i nterlead
flash
or protrusions.
i nterlead
flash
and
protrusions
shall
not
exceed
0.25mm
(0.010
i nch)
per
side.
5.
the
chamfer
on
t he body
is optional.
if
it is not
present,
a visual
i ndex
feature
must
be
located
within
t he crosshatched
area.
6.
is
the
length
of terminal
f or
soldering
to a substrate.
7.
i s the
number
of terminal
positions.
8.
terminal
numbers
are
shown
f or
reference
only.
9.
the
lead
width
b
as measured
0.36mm
(0.014
i nch) or greater
above
the
seating
plane,
shall
not
exceed
a
maximum
value
of
0.61mm
(0.024
inch).
10.
controlling
dimension:
millimeter.
converted
inch
dimensions
are
not
necessarily
exact.
index
a rea
e d n 12
3 -b-
0 .25(0.010)
c
a
m b s e - a-
l b m - c-
a 1 a sea
ting plane
0 .10(0.004)
h x 45
o c h 0 .25(0.010)
b
m m
|
